IMEC evaluates metal gates for <20nm scaling
Belgian semiconductor research lab IMEC is evaluating options for further transistor scaling using high-k dielectrics and metal gates in a replacement metal gate (RMG) integration schema.
“Although RMG technology is inherently more complex than gate-first integration, it has a number of advantages that allow increasing the device performance and that widen the choices in terms of high-k and metal gate materials,” said the lab.
One of the current challenges to enable further device scaling is the choice of gate dielectric and gate electrode.
For the gate electrode, key parameters are: work function, resistivity and compatibility with CMOS technology.
“Further scaling also requires continued improvement of channel mobility, adding options for improved stress management, and reliability control,” said IMEC. “In the industry, the RMG approach is rapidly becoming the integration scheme of choice, and an alternative for the gate-first approach.”
In RMG, the high-k gate dielectric is deposited in the beginning of the flow or just prior to gate electrode deposition and the gate electrode is deposited after the formation of junctions.
“A clear advantage is the enhancement of channel stress in shorter devices because of dummy-gate removal, an intrinsic step in RMG flow,” said IMEC. “RMG also allows metal gate processes with a lower thermal-budget, which broadens the range of material options for work-function tuning and reliability control.”
Additional advantages are lower gate resistance compared to gate-first, important for RF CMOS, claims the lab, and more room for mobility improvement.
As well as tool suppliers, IMEC’s partners in its core CMOS programs include: Globalfoundries, Intel, Micron, Panasonic, Samsung, TSMC, Elpida, SK Hynix, Fujitsu and Sony.
IMEC is presenting a number of papers at the 2012 VLSI Technology Symposium in Honolulu this week.