Revealed TSVs let chips slim to 50µm for 3D stacking
IMEC has introduced a ‘via-middle through-Si-via’ approach to 3D stacking.
“This method is new to industry as it allows to reveal through-silicon via [TSV] contacts by using a silicon etch process,” said the Belgian lab. “The process further allows thinning down the wafers to 50µm with a total thickness variation of less than 2µm.”
In the technique, copper-filled TSV contacts are buried in the wafer during front-side processing.
Once the wafer is finished, it is thinned from the back, revealing the flush ends of the TSV contact.
Great care has to be taken not to damage the devices during this initial thinning to 50µm and a key step is bonding the device wafer to a carrier wafer prior to thinning, by using a temporary adhesive.
“This material is stable during the subsequent process steps, but still allows for room temperature debonding of the thinned wafer upon completion of backside processing,” said IMEC.
A wet or dry etch now removes sufficient silicon to make the bottom ends of the vias stick up out of the back surface. This is the reveal step that IMEC speaks of.
“Chemical mechanical polishing [CMP] of the Cu/Si surface is not used as it results in a high risk of contamination and has a high cost-of-ownership,” said the lab. “An effective via reveal has been obtained using wet etching, exposing the TSVs uniformly on the wafer backside. In this stage, the TSV nails are still protected by their barrier and liner layers.”
The process ends with a Si3N4 backside passivation layer that blocks copper diffusion into the thin Si wafer, and with the liner layers on the TSV being selectively opened using a maskless, self-aligned dry etch-process.
“After this ‘soft’ via reveal process, further interconnect layers and bump interconnects can be processed on the wafer backside,” said IMEC. “Debonding the thin wafer from the carrier wafer and transferring the thin wafer to a dicing tape can now be performed at room temperature.”
The process has been demonstrated in a 300mm diameter wafer with active high-k/metal gate CMOS circuits.