SOI finfet will scale to 11nm, says Asenov

 

SOI finfets will scale to 11nm, according to Professor Asen Asenov, which means they will be useful for at least three generations of  process technology.  

 

“When you introduce a new device architecture you hope this will allow you to scale for several process generations – if it looks like it will only scale for one generation it is not a good investment.,” Asenov told EW, “we have shown we can scale SOI finfet for three generations – 22nm, 16nm and 11nm.”

 

Asenov’s group at GlasgowUniversity has shown that SOI finfets will meet the low statistical variability requirements of 11nm CMOS technology.

 

Asenov’s company, Gold Standards Simulations (GSS) worked with the university using the GSS statistical ‘atomistic’ simulator GARAND, which predicts physical simulation of statistical variability in modern transistors.

 

“In the war between future transistor architectures, predictive physical simulation of statistical variability can deliver significant competitive advantages,” says Asenov, “for technology providers, the decision of which of the competing architectures to adopt will be determined by the capabilities of the technology to deliver scaling benefits for at least two generations. GSS has a simulation tool chain that can facilitate these important decisions by providing not only accurate physical simulations of competing transistor architectures, but also accurate statistical compact model extraction and statistical circuit simulation tools that can help to understand their impact on design.”

 

Statistical CMOS variability introduced by discreteness of charge and atomicity of matter rules the CMOS world. Statistical variability in ‘bulk’ Mosfets, dominated by random discrete dopants, has dramatically increased device leakage and has slowed the scaling of supply voltage in the last four CMOS technology generations, fueling the power crisis. As a result statistical variability has become a major driver for the introduction of new, variability resistant, MOSFET architectures.

 

The variability crisis first impacted SRAM yield and leakage, which forced Intel to introduce FinFETs at 22nm.

 

“Intel announced in May that it would use finfets at 22nm,” says Asenov, “the hidden agenda behind this was because Intel was unable to scale its SRAM cell from 32nm to 22nm using bulk Mosfets. That’s why they were forced to introduce finfets “

 

Finfets tolerate lower channel doping when compared to conventional bulk mosfets and exhibit reduced statistical variability and associated CMOS leakage, says GSS, ‘Intel’s move has sparked the transistor wars between finfets and fully depleted (FD) SOI transistors, both claiming to provide a life-line FOR CMOS scaling which, otherwise, would stall.

 

Although the bulk finfets to be introduced by Intel are built on a conventional silicon substrate, finfets built on an SOI substrate could have significant advantages in terms of simpler processing, better process control and reduced statistical variability, states GSS.

 

“Intel have chosen bulk because it is the cheaper option but it has a lot of problems in terms of manufacturability and control,” says Asenov, “Intel was supposed to have 22nm at the end of this year or Q1 2012. Now this has been moved forward to sometime in 2012.”

 

Intel do not have a p aper at IEDM.  Usually if  Intel is introducing a new technology in the year they have a paper at IEDM

 

“Everyone is very curious that there is no paper from Intel about Intel using 22nm finfets,” said Asenov.

 

Glasgow University and GSS show that the statistical variability in ‘well tempered’ 10 nm SOI FinFETs can be kept below the statistical variability in 45 nm bulk CMOS technology.

 

Asked if there was any difference between what Intel calls a ‘trigate’ transistor and what the rest of the world calls a finfet transistor, Asenov replies: “Not a lot really. Trigate is a specific implementation of finfets. They use the word trigate as a differentiator.”

 

Asked if there were significant differences between finfets and full depleted SOI – the two main contenders to be the next mainstream IC transistor, Asenov replies: “Fully depleted SOI has very similar advantages to finfets.”


[1]   IEEE Spectrum, November 2011

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