The compiler supports the company’s low power, single port SRAM IP and dual port SRAM IP for 28nm FDSOI process technology. It offers capacities up to 1Mbit with word lengths up to 288bits and supports 4, 8 and 16 Mux factors.
According to the company it allows designers to make trade-offs between various SRAM sizes in terms of number of words, word length and multiplex factor, and automatically generates datasheets, simulation (Verilog), layout (LEF) and timing/power (Liberty) models to enhance and speed the design process.
The compiler is aimed at IoT and other applications that demand long battery life with minimal operating and stand-by power performance and will be valuable in the networking space where power and heat dissipation are critical.
The IP supports an operating voltage range of 0.6V-1.2V and dynamic power savings exceeding 50% of other commercial offerings, while The cutting static power by up to 35% with only a <10% area penalty, claims the company.
SureCore says it will follow the 28nm FDSOI compiler with a 40nm ultra low power compiler in March, that will target the leading foundry process. The company’s product roadmap also includes the introduction of a 40nm CMOS ultra low power SRAM later next year. Work also continues on a 28nm CMOS solution.
“There is still considerable innovation happening at relatively mature production nodes,” said sureCore‘s CEO, Paul Wells. “With the growing IoT market, mature nodes such as 40nm are 28nm are taking on an extended life. Their cost performance is ideal for the IoT technical and business challenges.”