Tech news tagged ‘EDA’

Synopsys looks to finfet design with new IC Compiler

Synopsys has introduced the 2014.09 release of its IC Compiler place and route product which has advanced support for finfet-based design.

Capabilities include look-ahead technologies, first introduced in the previous release of the compiler, and enhanced concurrent clock and data optimisation (CCD) for a frequency boost on…

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Mammal EDA and insect EDA

Bio-diversity is the future for EDA – with the mammals going one way and insects going another, says Chris Rowen, founder of Tensilica who sold his company to Cadence and is now CTO at their IP group…

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RTOS supports code reuse across ARM Cortex M cores

Mentor Graphics has a new version of its Embedded Nucleus real-time operating system (RTOS) which provides memory partitioning for all ARM Cortex M cores, facilitating code reuse.

By using the memory protection unit (MPU) on ARM Cortex M- based cores, the Nucleus RTOS process model creates memory partitioning without…

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Cadence tool for on-chip power sign-off

Cadence has introduced a transistor-level electro-migration and IR-drop (voltage drop) tool that delivers foundry-certified SPICE-level accuracy for power sign-off.

Called Voltus-Fi, it is intended complement Cadence’s Voltus IC power integrity tool, which is a full chip, cell-level power sign-off tool…

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Chip design has morphed into system design

EDA companies have become significant suppliers of silicon intellectual property (IP) Martin Lund, v-p of the IP business at Cadence tells Electronics Weekly about the importance of being more than an EDA tools company. 

Q: Why is a silicon IP business strategically important to an EDA tool supplier?


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Asenov sells statistical process IP to GloFo

Gold Standard Simulations (GSS), professor Asen Asenov’s IC production statistical analysis company, has signed a multi-million dollar contract to license its complete TCAD/EDA tool suite to Globalfoundries…

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Synopsys upgrades auto grade NVM IP

Synopsys has introduced non-volatile memory (NVM) IP for high-voltage processes used typically for automotive ICs.

Called DesignWare AEON Trim, NVM IP is designed to be compact and is available in standard 180nm 5V CMOS and Bipolar CMOS DMOS (BCD) processes without a need for additional masks or process…

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Chip design is crucial to Europe, says Cadence v-p

Alexander Duesener, v-p of worldwide field operations in EMEA for Cadence Design Systems believes chip designers have a crucial role in maintaining Europe’s strengths in wireless and automotive systems. The biggest challenge in complex SoC design is verification. How are designers in Europe tackling complex chip verification?Alexander…

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European chip design is vital for car industry, says EDA executive

Semiconductor design for automotive systems is an important and growing technology capability for European companies, according to Jean-Marie Saint-Paul, European director at Mentor Graphics. “Europe’s strong car industry is a big opportunity for the electronics design sector,” said Saint-Paul. It is important that Europe protect s…

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Enter the virtual lab for SoC verification, says Mentor

A “virtual lab” emulation environment can meet the challenges of complex SoC design verification, writes Richard Pugh of Mentor Graphics If you are verifying an SoC, you generally have three options when logic simulation runs out of steam – all based on hardware-assistance or acceleration. Yet these options have major…

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