Posts Tagged ‘EDA’

Chip design is crucial to Europe, says Cadence v-p

Alexander Duesener, v-p of worldwide field operations in EMEA for Cadence Design Systems believes chip designers have a crucial role in maintaining Europe’s strengths in wireless and automotive systems. The biggest challenge in complex SoC design is verification. How are designers in Europe tackling complex chip verification?Alexander…

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European chip design is vital for car industry, says EDA executive

Semiconductor design for automotive systems is an important and growing technology capability for European companies, according to Jean-Marie Saint-Paul, European director at Mentor Graphics. “Europe’s strong car industry is a big opportunity for the electronics design sector,” said Saint-Paul. It is important that Europe protect s…

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Enter the virtual lab for SoC verification, says Mentor

A “virtual lab” emulation environment can meet the challenges of complex SoC design verification, writes Richard Pugh of Mentor Graphics If you are verifying an SoC, you generally have three options when logic simulation runs out of steam – all based on hardware-assistance or acceleration. Yet these options have major…

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Tool offers mixed-signal design from HDL and Spice data

Tanner EDA has released version 16 of its HiPer Silicon full-flow design suite, offering a complete analogue and mixed-signal design flow from digital (HDL) and analogue (Spice, Verilog-A) electrical design and simulation, through synthesis to physical layout and verification.

New features and functionality include OpenAccess database support…

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Mentor introduces thermal analysis into the design flow

Mentor Graphics believes it is now possible implement thermal analysis of chips and PCBs at an early stage in the engineering design flow. The company aims to make thermal analysis of components, PCBs and enclosures part of the engineer’s design process and not the domain of thermal specialists. Mentor…

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Cadence plans to buy processor firm, Tensilica

Cadence Design Systems has agreed to acquire configurable processor IP company Tensilica for around $380m in cash. The acquisition will add processor IP used in mobile, infrastructure, in-car entertainment and consumer applications, to Cadence’s IP portfolio. “With Tensilica, we will be able to provide designers with a more…

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Cadence to buy Indian firm developing IP for finfets

Cadence Design Systems has agreed to acquire Cosmic Circuits Private, a developer of analogue and mixed signal intellectual property (IP) cores for the 40nm and 28nm semiconductor process nodes.

Bangalore-based Cosmic Circuits is also developing IP for 20nm and FinFETs.

“The combination of Cadence and Cosmic Circuits will…

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Atego opens up software reuse with internet database

Atego, the supplier development tools for safety-critical systems and software, has launched a database of software for publication and reuse.

Called Atego Asset Library, it is based on the OMG’s Reusable Asset Specification (RAS). The underlying database is suitable for all types of project assets. 

Atego Asset Library…

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Renesas uses coverage driven verification of automotive software

Renesas Electronics Europe has selected the verification tool suite of Coveritas for its automotive microcontrollers and systems-on-chip (SoC) software testing and verification. UK-start Coveritas only launched its first product in April 2012. This was a suite of coverage driven and constrained-random scenario based verification tools for…

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Cadence addresses double patterning in 20nm designs

Cadence Design Systems is targeting designs for the 20nm process node with its latest tools in the Virtuoso suite.

Called Virtuoso Advanced Node, the mixed signal chip design tool addresses 20nm design issues such as layout-dependent effects (LDEs), double patterning, colour-aware layout and new routing layers.

“Moving to…

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