Tech news tagged ‘IP’

Cadence releases IP for 3D memory

Cadence Design Systems is offering verification IP (VIP) supporting the design of 3D memory interfaces on standards including Wide I/O 2, Hybrid Memory Cube (HMC), High Bandwidth Memory (HBM) and DDR4 3D Stacking (DDR4-3DS).

The VIP models include direct memory access for read, write, save, pre-load and…

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Chip design has morphed into system design

EDA companies have become significant suppliers of silicon intellectual property (IP) Martin Lund, v-p of the IP business at Cadence tells Electronics Weekly about the importance of being more than an EDA tools company. 

Q: Why is a silicon IP business strategically important to an EDA tool supplier?

Martin…

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Asenov sells statistical process IP to GloFo

Gold Standard Simulations (GSS), professor Asen Asenov’s IC production statistical analysis company, has signed a multi-million dollar contract to license its complete TCAD/EDA tool suite to Globalfoundries…

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China manufactures $16trn debt

China’s massive manufacturing machine works on minuscule margins. Maybe, wonders David Manners, it would have been better if China had built up the quality of its educational system so that its own clever citizens could create the necessary IP to make more profitable products.

Has the China thing been…

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Comment: How to protect and maximise IP revenues

For electronics companies, knowing which intellectual property to protect and which can be used to generate additional revenue is important in driving value. CPA Global’s Haydn Evans explains how to make those assessments. Business is essentially about the commercialisation of ideas: how companies or individuals translate creativity and innovation…

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Synopsys gives Freescale verification route for SoCs

Synopsys is working with Freescale Semiconductor on verification of IP blocks for complex system-on-chip (SoC) devices. An aim of the collaboration, said the companies, is to achieve better schedule predictability and lower overall verification costs for complex SoCs. “Over the last few years, our designs have led a…

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Mentor targets silicon IP reuse with IJTAG tool

Re-use of IP blocks is an increasingly impartant element of embedded design, says Mentor Graphics. The design software firm has introduced a tool which will make it simpler to reuse test, monitoring and debugging logic embedded in existing IP blocks. “The continued exponential growth in semiconductor device functionality and…

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Most powerful mini-8051?

Polish IP firm Digital Core Design has put an 8051 CPU into under 3,000 asic gates, claiming it to be the most powerful at this size. “A very low gate count area allows as well to run the core at high performance, up to 300MHz in Hynix 0.18…

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Mentor sees need for manufacture-compliant chip IP

As IC dimensions fall below 65nm, manufacturing variability makes it more difficult to predict yield for any particular design. Design for manufacture-compliant IP is a growing necessity, writes David Abercrombie Design for manufacturing (DFM) techniques were developed precisely to help design houses create IC designs that yield well in…

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