Posts Tagged ‘process’

Cadence and TSMC open door for volume 3D-IC production

Cadence has announced that its 20nm and 3D-aware technologies are qualified for two TSMC reference flows. Specifically, new 20nm capabilities in the Cadence Virtuoso and Encounter platforms have been certified for the TSMC 20nm Reference Flow. 

Cadence 3D-IC technologies (including our IP for Wide I/O) have been…

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Ho Chi Minh City plans fab

The Vietnam government is planning to set up a fab, following the establishment of a programme called ‘Development of the IC industry of Ho Chi Minh City.’

The programme envisions founding chip company start-up incubators, design and prototyping facilities and a fab.

By 2017, the programme expects to have…

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ARM and TSMC work on first finfet processors

TSMC and ARM have extended their chip making technology collaboration beyond 20nm technology to deliver ARM processors on finfet transistors.

The first ARM processor to use finfet transistors will be the 64-bit ARM processors based on the ARMv8 architecture. TSMC will use the ARM processors and technology to benchmark…

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ST tapes out first 20nm test chip with Cadence’s help

Cadence Design Systems announced that its tools were used by STMicroelectronics for the tape out of a  20nm test chip, incorporating custom analogue and digital elements in a SoC design.

Engineers from the two companies collaborated closely to develop technologies and deploy methodologies using the Cadence Encounter and Virtuoso platforms…

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Sagantec buys Dutch specialist in 20nm design rules

Sagantec has acquired Netherlands-based start-up NP-Komplete Technologies which specialises in design for manufacture (DFM) and physical design optimisation.  

The Eindhoven-based start-up brings to Sagantec its physical design compaction and migration tools based on a 2D dynamic compaction technology.

“The NPKT migration technology is an automated…

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ISSCC: IMEC and Holst bio chip gets accolade

A biopotential acquisition chip from IMEC and its Netherland partner Holst Centre has been singled out for praise at the International Solid-State Circuits Conference in San Francisco. “There has been a growing interest in wearable biopotential-monitoring systems, which have very strict requirements in terms of power dissipation, high…

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Samsung works with Cadence on design flow for 28nm

Samsung Electronics’ foundry business has collaborated with Cadence to develop a design-for-manufacturing (DFM) infrastructure.

This involves the development of “in-design” and signoff DFM flows to tackle physical signoff and electrical variability optimisation for 32-, 28- and 20nm system-on-chip (SoC) designs.

According to the firms, the…

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Magnets fix superconducting plate in levitation

Surely if flying saucers existed, they would float around like the disc in this video. The demonstration by physicist Boaz Almog from Tel Aviv University, Israel, at the Association of Science-Technology centres (ASTC) Annual Conference in Baltimore, Maryland, earlier this week illustrates how a superconducting plate can be fixed…

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UMC and Cypress see first 65nm embedded flash chip

United Microelectronics Corporation (UMC) has produced first working silicon on 65nm using a silicon oxide nitride oxide silicon (SONOS) process that supports embedded flash memory. The development of this 65nm embedded flash process is the result of collaboration with programmable chip firm Cypress Semiconductor. Cypress plans to use the embedded…

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ST, CMP make 28nm available for MPW.

STMicroelectronics and the multi-project wafer organisation CMP (Circuits Multi Projets) have announced that the CMOS 28nm process from STMicroelectronics is now available for prototyping to universities, research labs and companies through the silicon brokerage services provided by CMP.

 
The introduction of the 28nm CMOS process builds on the…

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