Verification is key as automotive chip design goes 28nm

IC design house Sondrel says that automotive SoC design is now starting to focus around  the 28nm process node.

Verification is key as automotive chip design goes 28nm

This is now a well-established and high yield node and so will support the automotive sector’s need for dielectric isolation (leakage current v speed trade off).

This will mean that IC designers must address the design rules associated with:

  • High Temperature Operating Life (HOTL)
  • Automotive Safety Integrity levels (ISO26262 ASIL A-D)
  • Testing the design to a reliability prediction program, (SN29500/TR62380)

Sondrel says that designers must start as early as possible in the design process with a robust verification strategy.

It has described the key verification and design for manufacture techniques in a white paper:

  • Functional Verification
  • Formal Verification Techniques
  • DfT for Automotive
  • DFM aware Physical Design
  • ESD Design Technique
  • Power Management

Sondrel writes:

“Current verification methodologies, such as SystemVerilog, assertion based verification (ABV), UVM and metric driven verification, will help you to “shift left” in the design process. Each of these technologies increases productivity and underpins the successful compliance to automotive standards.

“In addition, the latest DfT techniques should be applied to increase the testability of the design and reduce production test times. To meet the quality and reliability requirements of the ISO 26262 and other automotive electronics standards inserting Logicbist will enable infield and system testing throughout the product life cycle.

“It can also be used for fast manufacturing test bring up, thereby reducing expensive test time. Internal JTAG P1687 is also an important consideration. Internal JTAG replaces ad-hoc communication methods for controlling on-chip test structures and embedded instruments enabling higher degrees of interoperability and DfT re-use.

“Thirdly, considerations for the Physical Implementation of the SoC. Using the correct software tools is vital as it will give you the necessary design checking, version management, register generation and documentation support adherence to regulatory compliance mandates such as DO-254 and ISO 26262.

Another important consideration is the the analysis and fixing of any EM (Electro Migration ) issues. Encompassing all of your design efforts, a fit for purpose design flow will enable the physical implementation of the SoC to meet and achieve challenging customer PPA and DFM targets.

You can download a Sondrel datasheet on this subject here

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