Toshiba has expanded its digital TV ICs with an H.264/VC-1 video decoder which is designed to work with an external scaling and processing IC, with data shared between the two via a PCI bus. It is controlled by the external companion IC with a PCI bus.

The chip supports the H.264 video decode, high profile at level 4.1, and the VC-1, advanced profile at level 3.

The decoder takes the video MPEG TS packet stream from the companion IC and return the decoded video data along with clock and vertical/horizontal synchronisation information. A PCI controller and a 33.3MHz PCI interface provide for the communication of command and control signals with the companion IC.

The TC90490XBG is based on a dual bus architecture and features an integral DMA controller and clock generators. A built-in DRAM controller supports a 32-bit, 200MHz connection to external DDR-SDRAM.