Lattice Semiconductor has a low power XAUI/ HiGig/HiGig+ to SPI4.2 programmable interface which is implemented in its LatticeSCM FPGA range.

It uses the LatticeSCM device’s system packet interface level 4 phase 2 (SPI4.2) hard IP capability, and includes a 10Gbit Ethernet media access controller (MAC) soft IP core. The chip is designed to offer an interface between the serdes-based XAUI standard, typically used in 10G Ethernet networks, and the SPI4.2, parallel bus interface used by network processors. 

When implemented in a SCM-15E FPGA packaged in a 256 fine pitch BGA package, the bridge requires a board area of 17x17mm and consumes 2.5W.

The SCM devices also include from 4- to 32-channels of serdes supporting data rates from 600Mbit/s to 3.8Gbit/s.

While the flexiPCS physical coding sublayer block embedded in the devices supports an array of comms data protocols, including Gigabit Ethernet, Fibre Channel, 10 Gigabit Ethernet (XAUI), PCI Express, Serial RapidIO and SONET/SDH. 

The IP is available as a XAUI to SPI4.2 IP bundle downloadable from the company website.