Lattice Semiconductor has announced the interoperability of its ECP2M FPGA family with the Linear Technology LTC2274, 16-bit, 105Msample/s, ADC in support of the JESD204 high-speed serial specification from the JEDEC group. 

According to Stan Kopec, Lattice v-p of marketing: “By working together with Linear Technology, we were able to demonstrate how this interface dovetails perfectly with the integrated, high-speed serdes channels offered on the LatticeECP2M family of FPGAs.”

The aim is to provide a lower power and smaller footprint design for the interface between data converters and FPGA devices.