Sundance has extended its partnership with IP firm Cadre Codesign to offer the firm's CT-JPEG04 core across a range of its modular DSP FPGA multiprocessor hardware systems. 

Based on the JPEG ISO/IEC IS 110918-1 standard image-compression algorithm, the core compresses images of 1280x1024 pixels resolution at a rate of 500frames/s and can sustain an input of one 8-bit pixel every 660MHz. 

Built on Sundance's modular and infinitely-scalable multiprocessing platform, the DVIP incorporates two TI TMS320C6455 digital signal processors and a TMS320DM642 DSP-based digital media processor.

The 1GHz C6455 DSPs allow multiple processors to be connected via a Serial Rapid I/O (SRIO) interface and the DVIP incorporates Xilinx Virtex-4 FX60 FPGAs that are the implementation target for Cadre's CT-JPEG04 core.

According to Pierre Popovic, Cadre Codesign's president, a key issue facing developers who use conventional systems is storage of the 524Mbyte/s (monochrome) or 1.535Gbyte/s (colour) outputs generated by high performance cameras. "This is compounded by bus technology that struggles to sustain more than 250Mbyte per second.  By marrying our CT-JPEG04 core with FPGA technology we provide an optimal compression solution that overcomes the bus bottleneck and storage problem," said Popovic.

See http://www.sundance.com