Toshiba Electronics Europe’s is offering two mixed-signal IP cores designed to simplify and speed integration of LVDS (low-voltage differential swing) transmitter and receiver functionality into system-on-chip (SoC) designs for flat panel display (FPD) applications.

The dual link LVDS transmitter (FPD-TX) and the LVDS receiver link (FPD-RX) are mixed-signal, hard macros that provide high levels of functionality and flexibility. These IP blocks are silicon-proven and are optimised for Toshiba’s TC320 ASIC technology, ensuring seamless and rapid integration into SoC designs based on this 65nm 1.2V low-power process.

Toshiba’s FPD-TX LVDS transmitter IP provides the functionality needed for dual link transmission from a host SoC to the flat panel display and is designed for FPDs with resolutions up to UXGA.

The IP block can convert up to 60 bits of RGB picture signal data and up to 12 bits of control signal data into 10 or 12 LVDS streams. Operating at dot clock frequencies from 25MHz to 85MHz, the FPD-TX combines integrated high-speed clock generation and a selectable frequency range to minimise the need for external components.

The FPD-RX LVDS receiver IP is designed for FPD signal streams with resolutions up to SXGA+ and also offers a selectable frequency range to optimise performance in the target application. The cell receives synchronous data along with the corresponding pixel clock information via an LVDS interface.

More information: www.toshiba-components.com/ASIC