Mentor Graphics has released a PCB power integrity tool.
"It analysises power planes for DC drop, and it does AC analysis to see more decoupling capacitors are needed to reduce noise," Mentor director of market development John Issac told Electronics Weekly.
Called HyperLynx PI (power integrity), it is designed to work with the firm's own PCB layout tools, as well as those from companies including Altium, Cadence and Zuken.
"We have advanced users today that are required to design over 30 power delivery structures into a single PCB, driven by the multiple voltage levels and power requirements of their ICs," said Henry Potts, v-p of
"With accurate analysis, the power and ground plane structures and de-coupling capacitor number, as well as placements, can be determined, thus avoiding over-conservative design."
Designer can determine the number and location of decoupling capacitors, or experiment with the PCB fabrication materials and stack-up to determine the best electrical and cost solution.
The tool produces 2D plots of the power planes, coloured to indicate current density or other chosen parameter. Other output formats include psudo-3D histograms and listings.
"There are several levels of computation," said Issac. "A first-order estimate comes in seconds. Some more complex designs can take 15 minutes to half an hour for the exact geometry of every via hole to be accounted for."
To use the tool, every chip model has to include additional data that indicates what DC power flows into its power pins, supply voltage tolerance, and which output pins switch when. Output switching is used by the tool to estimate current transients at the power pins.
"We have really focused on making the information easy to put in," said Issac, and chip vendors, as usual led by FPGA companies, are producing libraries to go along with their products.
Selected customers are already using the tool, which goes on general release "probably at the end of Q1", said Issac.
More information: http://www.mentor.com/hyperlynx
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