Xilinx says that its latest generation Virtex-6 FPGA family is compliant with the PCI Express 2.0 specification.

The second-generation PCIe block integrated in Virtex-6 FPGAs has passed PCI-SIG PCI Express version 2.0 compliance and interoperability testing for 1 to 8-lane configurations.

Xilinx has also teamed up with alliance members Northwest Logic and PLDA to provide Direct Memory Access (DMA) intellectual property (IP) cores for Virtex-6 FPGAs.

This follows an existing PCIe 2.0 soft IP for Virtex-5 FXT devices, the first FPGA to provide PCIe 2.0 x8-lane support with the Northwest Logic DMA core.

DMA engines enable the efficient movement of data in systems, ensuring that the PCIe block in Virtex-6 FPGAs delivers maximum performance and bandwidth.

Designers can immediately begin the evaluation and design of PCI Express 2.0 compliant systems in Virtex-6 FPGAs. To assist in this effort, the Xilinx CORE Generator system delivered in the ISE Design Suite provides the PCIe core, reference design and all the scripts, basic testbench, and simulation models needed to streamline integration into customer designs.