Lattice Semiconductor has available eight new reference designs, a $49 development kit for the ProcessorPM POWR605 power manager device and a $69 development kit for the ispMACH 4000ZE CPLD, the ispMACH 4000ZE Pico development kit.

The ispMACH 4000ZE family offers typical standby current as low as 10µA; 0.4mm pitch Ball Grid Array packages; 3.3V, 2.5V and 1.8V I/O standards support; and 5V tolerant I/Os.

Lattice’s ispMACH 4000ZE CPLDs can be used for power management, level shifting and general purpose I/O expansion.

The ProcessorPM (Processor Power Manager) POWR605 device monitors up to six circuit board power supplies and provides up to five open-drain digital I/Os. 

The device can generate signals such as a CPU Reset, including pulse stretching and power supply fault interrupt, using the on-chip 16 macrocell CPLD and four programmable timers. 

There are also two general purpose digital inputs, which can be used for other control functions such as manual reset input and watchdog timer input.  The ProcessorPM device is available in a 4x4mm, 24-pin QFNS package.