Lattice Semiconductor has announced version 8.0 of its ispLEVER FPGA design tool suite, which is used for the design of high speed double data rate (DDR) interfaces for the LatticeECP3 FPGA family. 

Lattice Semiconductor has also said that it will collaborate with Beyond Semiconductor in the development of compiler tools for its soft processors, the LatticeMico8 and LatticeMico32 embedded microprocessors.

The IPexpress tool can be used to generate the HDL for the most appropriate generic DDR interface based on user requirements such as direction, speed and bus width. 

There is now automatic interface code generation to increase design productivity and reduce coding errors, as well as enhanced timing analysis that provides more transparency to circuit timing details.

More information at: http://www.latticesemi.com