Lattice Semiconductor has announced availability of Service Pack 1 for Version 8.0 of its ispLEVER FPGA design tool suite.

This updates the device values to production characterized silicon for the LatticeECP3-150EA device. 

With SP1, static timing analysis, timing simulation and power calculation will report results that reflect the behaviour of the actual production device. 

Moreover, PCS/SERDES calibration settings used for the supported IO protocols have been tuned to provide more robust behaviour, said the supplier. 

HDL generation of generic DDR interfaces from the IPexpress tool, first introduced in ispLEVER 8.0, has been enhanced to include two additional interfaces, resulting in more design and implementation flexibility. 

There is also additional flexibility in the choice of pins for generic DDR interfaces.