Lattice Semiconductor’s ispLEVER Classic design tool has been upgraded with the addition of Synopsys Synplify Pro with the HDL Analyst feature set.

Version 4 of the design tool also has an improved ispMACH 4000ZE CPLD fitter with improved power optimisation.

Synplify Pro HDL Analyst can be used to visualise high-level register transfer level (RTL) Verilog or VHDL. 

Designers can cross-probe between the graphical diagrams and source code to ensure that the coding style they use is the most efficient for the target CPLD.

Finite State Machines (FSM), for example, are popular functions designed into CPLDs.  FSMs are automatically extracted by HDL Analyst and displayed graphically as a bubble diagram with state transition arrows and a table of state encodings.

Users can download, for free, ispLEVER Classic for Windows, as well as the optional Synopsys Synplify Pro logic synthesis and Aldec Active-HDL simulator modules.