Bread Crumb Menu
-
You are in:
- Home
- Products
- Test & Measurement
Saturday 26 May 2012
Products
Test & Measurement
JTAG Tech cuts cost of entry for boundary scan
Friday 8 October 2010
JTAG Technologies is aiming to reduce the cost of boundary-scan test and programming with its ProVision Designer Station offering a lower entry price.
Providing automatic test program generation (ATPG) for interconnections and in-system programming (ISP) for devices, the ProVision Designer Station includes a scripting library known as JFT (JTAG Functional Test) based on the open-source Python language.
It can be used to add test options for logic clusters and for the programming of memory devices.
A serial vector format (SVF) player feature serves as a programmer for CPLDs and FPGAs, and the system also includes the sequencer module ‘AEX Manager.’
Providing automatic test program generation (ATPG) for interconnections and in-system programming (ISP) for devices, the ProVision Designer Station includes a scripting library known as JFT (JTAG Functional Test) based on the open-source Python language.
It can be used to add test options for logic clusters and for the programming of memory devices.
A serial vector format (SVF) player feature serves as a programmer for CPLDs and FPGAs, and the system also includes the sequencer module ‘AEX Manager.’
Site Navigation
Active suppliers
Agilent Technologies
Analog Devices
Harting
LEM
Maxim Integrated Products
NXP
Rohde & Schwarz
Tektronix
Toshiba
Yokogawa
Search for a supplier
Blogs on EW
Mannerisms
Chip industry musings from David Manners
On AirViews from a UK technology startup
Made by MonkeysAnalysis of bad designs
Gadget MasterBuild ingenious inventions, win £250
Distribution WorldLatest distribution news and views
Directive DecoderGary Nevison on industry legislation
Electro-RamblingsEW website blog, highlighting new content and features
Chips and BeerOut on the far flung semiconductor trail