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Saturday 26 May 2012
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Digital ICs
Averlogic FIFOs designed for HD video capture
Monday 24 October 2011
2001 Electronic Components has renewed its partnership with Averlogic and is offering the supplier’s AL460 HD FIFO for processing large quantities of HD data for video capture applications.
The FIFO’s design overcomes issues of pin count which can limit frame buffers found in FPGA designs.
According to the supplier, FPGA implementations requiring higher I/O pin counts can place demands on logic resources and property memory controllers, forcing a designer to move up to higher grade FPGAs.
AverLogic’s HD-FIFO is designed to reduce I/O pins and logic resources, at the same time overcoming latency issues.
The I/O is programmable and the device has a double buffer mode to reduce FPGA overhead.
www.2k1.co.uk
The FIFO’s design overcomes issues of pin count which can limit frame buffers found in FPGA designs.
According to the supplier, FPGA implementations requiring higher I/O pin counts can place demands on logic resources and property memory controllers, forcing a designer to move up to higher grade FPGAs.
AverLogic’s HD-FIFO is designed to reduce I/O pins and logic resources, at the same time overcoming latency issues.
The I/O is programmable and the device has a double buffer mode to reduce FPGA overhead.
www.2k1.co.uk
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