We all know how important memory speed is for fast computers. Whereas memory interface was traditionally defined for desktop PCs, now the drive is for faster mobile memory, and that means keeping power consumption in check too.
Smartphones and tablets, driven by the needs of Samsung and Apple are changing the memory interface game, dramatically.
The speed of development of smartphone apps processors is forcing the pace for memory design. The ink was barely dry on the previous generation LPDDR3 specification before it was decided that application, such as retina displays, would need more than LPDDR3’s 2Gbit/s data rate.
The JEDEC standards committee started work on the new mobile DRAM specification last year and with unprecedented speed it is expected to be finalised by the middle of this year.
In the mobile world, fast memory bandwidth is not only defining processing speed. It is also defining screen resolution. And this is why smartphone makers are racing to adopt LPDDR4.
A 1920×1080 resolution display may need a 3.2Gbit/s of memory bandwidth.
Apple could be implementing it in next generation iPads by the autumn. This is a very fast rate of adoption for something as detailed as a memory interface specification and chip suppliers and silicon IP vendors are racing to keep up.
LPDDR4 is the latest generation of the high speed memory standard, designed to combine high data throughput with power efficient operation for smartphones and tablets.
The JEDEC standards body is expected to publish the specification this year.
“Memory is playing an important role in the increased functionality and performance of mobile devices such as smartphones and tablets,” said Mian Quddus, chairman of the JEDEC board of directors.
“LPDDR4 and Wide I/O 2 are key new standards for memory interfaces,” said Quddus.
LPDDR4 will effectively double the data bandwidth of its predecessor LPDDR3 to achieve 4.12Gbit/s.
Wide I/O mobile DRAM is very much a high bandwidth memory interface for 3D gaming and HD video, with 1080p H.264 video, pico projection.
It uses chip-level three dimensional stacking of memory chips interconnected with through silicon via (TSV) links. Memory bandwidth is up to 17Gbyte/s.
LPDDR4 specifies a 1.1V VDD to lower power consumption. This could also ultimately drop to 1.0V.
This is not just a speeded up version of LPDDR3. In order to achieve the increase in speed, a doubling of data rate, and power saving, a 40% power reduction, it has been necessary to define a new memory architecture for LPDDR4.
It specifies a two-channel x16 DRAM, which is intended to reduce internal DRAM die power. There is also a lower voltage logic signalling scheme, defined at 350mV (peak-to-peak) with configurable termination and data bus inversion for better signal integrity.
Pin-count has also been lowered to 6-pins by using CA encoding.
This is very much future technology. Most smartphones today use LPDDR2 (1Gbit/s) and LPDDR3 (2Gbit/s) mobile DRAM devices.
Apple is expected to uses LPDDR4 memory chips in its 2014 iPad, iPhone and Mac models.
Micron, SK Hynix and Samsung are racing to get into production of LPDDR4 mobile DRAM in time for the needs of Apple.
Samsung, which proposed the lower voltage logic signalling scheme, has announced an 8Gbit LPDDR4 mobile DRAM fabricated on a 20nm process.
As a result the typical four-die mobile memory package will be able to offer 4Gbyte of memory in the same physical footprint.
Cadence is offering verification IP (VIP) models for LPDDR4 memory that support third party simulators, verification languages and methodologies.
Synopsys has recently introduced intellectual property (IP) for LPDDR4 including a multiPHY, DDR memory controller and verification IP (VIP).
The LPDDR4 IP supports 3,200Mbit/s data rate performance needed for fast processors, high-resolution displays, HD video and graphics-intensive games in mobile system-on-chip (SoC) applications.
There are also power-saving features such as low-power modes (including power-down, self-refresh, and deep power-down), clock gating and power down of sections of the PHY that are not in use at a given moment.
A feature of the LPDDR4 IP is its support for a split PHY implementation to permit designers to distribute the IP around the SoC, optimising the interface for PoP assembly.
“Designers can take advantage of Synopsys’ DDR hardening and signal integrity services to harden the LPDDR4 multiPHY and to analyse the signal integrity of the entire system (silicon, package and PCB), easing IP integration and reducing potential risks in the use of advanced manufacturing technologies,” said the supplier.
There is backward compatibility with LPDDR3 and DDR3/4 SDRAMs.
The DesignWare Enhanced Universal DDR Memory Controller IP with support for LPDDR4 is available now. The DesignWare LPDDR4 multiPHY IP is scheduled to be available in Q3 2014 in a leading 16nm FinFET process technology.
Verification IP for LPDDR4 is scheduled for early availability in Q3 2014.