Clearing Up The Node-Naming Mess

“Let’s clear up the node naming mess,” says Intel’s process guru Mark Bohr.

He proposes a density metric Gordon Moore would approved of – the number of transistors per square millimetre.

Nice and simple.

But then Bohr goes on to add ‘weighting factors’ and comes up with a formula for measuring transistor density which is not simple:

0.6 x NAND2 Tr Count + 0.4 x Scan Flip Flop Tr Count = # Transistors/mm2.

A simpler approach to clearing up the node naming mess might be to name a process after its minimum feature size.

It seems that the features on Intel’s 10nm process measure:

34nm fin pitch
53nm fin height
36nm minimum metal pitch
272nm cell height
54nm gate pitch

Nothing there about anything measuring 10nm.

Gordon Moore was a much greater scientist than anyone Intel has today, and he explains things simply.

What Moore said in 1965 was: “The complexity for minimum component cost has increased at a rate of roughly a factor of two per year.”

Nice and simple.

How Intel quoted it this week is: ‘The number of transistors and resistors on a chip doubles every 24 months.”

The change in timing is OK, Moore acknowledged that later on, but why does a company’s marketing department make up a quotation from its co-founder? It seems pointless, and it discredits Intel.



  1. I agree with DontAgree too Steve, in fact I very often agree with DontAgree and it’s definitely possible.

  2. If the metric is going to be nand2, then it will take about 2 second before every library will have a infinitely small (and unusable) nand2 purely for the purpose of scaling bragging rights … which is no different than we already have, so why bother.

  3. I agree with you Gary. Bohr does acknowledge the SRAM-based metric but in a rather opaque way: He says: “Given the wide variety of SRAM-to-logic ratios in different chips, it is best to report SRAM cell size separately, next to the NAND+SFF density metric.”

  4. I think they should base node on SRAM cell size. It seems to be the only thing that has consistently scaled with node changes, before and after gate length scaled with node change. The SRAM area dominates SOC chip area, and it appears to me the process changes are being made to maximize the SRAM area reduction (~50%) at each node change despite minimum geometries which have not scaled since ~130nm node.
    It aligns with Bohrs idea of transistors per sq mm (Since SRAM have for 30+ years been 6T) without the complexity of the ‘weighting factors’.

  5. Right on, Steve, way cooler, as you say.

  6. I’m just waiting for the first semi vendor to start expressing gate length (which is what that node number is supposed to be, but no longer is) in angstroms (Å) instead of nm. Looks way cooler and the unimpressive 1nm drop from 3 to 2 nm looks way better as a 10Å difference, don’t you think?

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