Learn more from Fujitsu Semiconductor at Embedded Live 2010 which takes place at Earls Court, London 20-21 October.
Implemented in a high-performance 0.9V 40nm CMOS technology, the 65GSa/s ADC demonstration chip has power dissipation for a single channel of 1.2W.
This is 50% less than previous ADC which was fabricated on a 65nm process.
“With this architecture, the ADC is no longer the limiting factor on speed and power,” said Ian Dedic, chief ¬engineer of Fujitsu’s communications business unit.
The ADC has been designed by ¬Fujitsu’s mixed-signal development group in Maidenhead. It is designed on the firm’s CHArge-mode Interleaved Sampler (CHAIS) architecture, which is based on a four channel dual polarisation QPSK sampling scheme.
There is x2 over-sampling and so there is a need for considerable DSP on chip. This is around 30Tera operations per second.
According to Dedic, the single -chip design is the only way with this speed of device. Data throughput can be 1.3 to 1.8Tbit/s and it would be too power-costly to take signals at these speeds off chip.
“Effectively we have put the ADC design on the digital roadmap and it is now the speed and power consumption of the DSP which will be the limiting factor for future devices,” said Dedic.
The track and hold circuits run very fast – less that 9ps to acquire the signal and 9ps to transfer to the next stage in the interleaving process.
The sampling circuits have a 16GHz bandwidth and the on-chip phase-locked loop generates as little as 30fs jitter.
At these frequencies the signal skew on the channels is critical. Fujitsu’s design uses a technique whereby the matching is carried out with the ADC in operation by analysing the signal outputs and calibrating the samplers.
“We are now matching the interleaved channels to within 100fs,” said Dedic.
Embedded Live 2010 is now taking delegate registrations for the UK exhibition which takes place at Earls Court, London 20-21 October 2010.