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Although the MIPS64 instruction set has been licensed in the past, it is less common for the complete core to be licensed in RTL form.
Remarkably, the 64-bit core will be half-way down the firm’s performance range – and will be the first of its I-Class Warrior processors.
In order of performance, its current (Warrior) core range is M-Class (five-stage pipeline), I-Class (nine-stage, multi-thread, dual issue), and P-Class (16-stage pipeline, out-of-order execution, multi-issue).
These grew out of the microAptiv, interAptiv, and proAptiv MIPS cores released before Imagination bought MIPS Technologies last year.
Warrior cores combine MIPS’ CPU expertise with Imagination’s knowledge of parallel processing from its PowerVR graphics processors.
Current 32-bit P-Class processors (3.5DMips/MHz) will outperform the 64-bit I-Class core (2.3DMips/MHz single-thread, 3DMips/MHz multi-thread), but raw performance is not what this core is about.
“There are some things 64-bit architectures are better than 32-bit architectures at, like data moves, data manipulation, and compute on large data types. But the reason most people move to 64-bit is addressable memory space,” Imagination director of business development Mark Throndson told Electronics Weekly. “32-bit only addresses 4Gbyte and, because of segmentation, it is normally significantly less than 4Gbyte. Android already takes around 1Gbyte, and can go well over 1Gbyte.”
Just to complicate things further, all Warrior M and P cores so far have been built to execute the two-year-old Release 5 MIPS64/32 instruction set. The first 64-bit core, the I-Class I6400, will execute Release 6 of the instruction set, as well as un-modified 32-bit Release 5 and 6 code.
“We looked at the way cores were being used, with loads like position-independent code,” said Throndson. “So we added instructions that are better for the just-in-times, virtual machines, Java Script, browsers, position-independent code for Android, and abstracted compilers like LLVM.”
I6400 is also designed for massively parallel configurations.
The minimal configuration is a one single-threaded core.
Up from there is a single core executing two or four treads – these are Imagination’s first MIPS cores with hardware multi-threading. They also have hardware virtualisation, and 128bit SIMD (single-instruction, multiple data).
Then comes multi-core configurations with two to six cores, coherent at the L1 cache level, with any or all cores single, dual- or quad-threaded. Imagination calls this a 2-6 core ‘cluster’.
After this it gets really parallel as up to 64 clusters can be implemented in parallel, all coherent at the L2 cache level. Maximum configuration is 265 cores running 1,024 threads.
Modelling, which Throndson is confident will prove accurate, indicates a 1GHz core will occupy 1mm2 on TSMC’s 28HPM (28nm) process, and hit 5.6CoreMark/MHz and 3.0DMips/MHz. This is with 32kbyte instruction and data caches, two threads per core, SIMD, floating point, and hardware virtualisation with 15 guests. In a preliminary chip floor plan, four of these cores have been positioned with 1Mbyte of L2 cache and 128 virtualised interrupts.
