1Gbit double data rate memories rise to the challenge of Rambus

1Gbit double data rate memories rise to the challenge of RambusRichard Ball  
 
Just to prove that Rambus won’t have it all its own way in the future, the DRAM session at ISSCC outlined three papers for double data rate synchronous memories with 1Gbit capacity. Only one paper, a 72Mbit device from Toshiba, featured a Rambus interface.
Double data rate (DDR) is fast emerging as a viable future competitor in the DRAM market for many applications, particularly servers and workstations. The three 1Gbit papers came from NEC, Samsung and IBM/Siemens.
The IBM/Siemens chip incorporates a hybrid bit line architecture in order to reduce the amount of non-memory cell transistors. 512 cells are connected to each local bit line (LBL). Four LBLs are multiplexed to each sense amplifier (see diagram). Two lines (the HBLs) pass over the LBLs using a higher metal layer. This multiplexing alone reduces chip area by six per cent.  
  In IBM and Siemens’ 1Gbit DRAM, die area is saved by multiplexing four bit lines into each sense amplifier. Differential data from the memory cells is selected by the relevant word line and passed to the amplifier.
The efficiency of the layout in terms of memory cell ratio is 67.5 per cent. This is 15 per cent higher than a conventional chip. Along with some other changes, the hybrid bit line architecture drops the total die area from 460mm2 to 390mm2 in a 0.175?m CMOS trench process.
During burst mode, running at 200MHz, each data output can run at 400Mbit/s. Thus a x16 organised device has a data rate of 800Mbyte/s.
Samsung has ended up with a 349mm2 die size for its 1Gbit SDRAM by using a 0.14?m process. The paper focuses on the timing requirements for this size and speed of memory.
To reduce skew, data flight time (time from pad to pin) has been reduced by having more of the signal trace on the outside of the package. The RC time constant for the external package track is smaller than the internal chip track, so flight time is reduced by 29 per cent.
Overall the Samsung chip outputs data at 333Mbit/s/pin (a 167MHz clock).
NEC’s paper, with no less than 28 authors listed, features a 250Mbit/s/pin, 1Gbit DDR SDRAM, with a two-cycle-lock clock generator running from 25 to 167MHz.


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