Actel FPGAs at CPLD speed

Actel FPGAs at CPLD speed
Steve Bush Actel has introduced a fast FPGA family which it claims can compete with complex programmable logic devices (CPLDs) on their home ground of address decoding. “For the first time there is an FPGA that is fast enough to integrate functions normally reserved for CPLDs alongside more usual FPGA blocks,” said Bruce Weyer, Actel’s product marketing director. Called the SX FPGA family, it has a claimed pin-to-pin delay of 6.6ns for a 25-bit decode. This, Weyer believes, will out-perform CPLDs in some applications: “A 5ns CPLD will certainly decode 16-bits in 5ns, but it takes at least 8ns for 24-bits as another level of logic has to be bought in. And you can fit the contents of 16 32-macrocell CPLDs on a single A54SX16.” For more traditional FPGA applications which are register-based, performance is also said to be good. For instance, clock to out delay is 4ns on SX chips. “This is the fastest among FPGAs and CPLDs on the market,” said Weyer. “Cisco has already used an SX FPGA to produce a 66MHz PCI bus arbiter which handles PCI data at a sustained 50MHz.” Actel’s FPGA technology is based on anti-fuses, a one-time programmable technology. The difference between SX and earlier families of Actel FPGAs is that anti-fuses are now available between metal layers two and three, as well as one and two. “Along with moving from 0.45 to 0.35?m technology, this has saved us 50 per cent space on the die.


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