Agile hardware uses multi-level FRAM

Agile hardware uses multi-level FRAMSteve Bush  
 
Ferroelectric RAM(FRAM) is featured in several ISSCCpapers.
FRAM has long been mooted as ‘the’ future technology for unifying memory in products like mobile phones. This is because it is non-volatile and fast in both read and write modes making it suitable to replace RAM, flash and EEPROM memories in one go.
One particular paper took the concept a step further and examined the potential of multi-level FRAMto produce agile hardware for portable products that combines the characteristics of FPGAs and microcontrollers while consuming little power.
Conventional reconfigurable hardware internally employs a memory such as SRAM, DRAMor EEPROM to store its logic configuration. Of these, SRAM and DRAM are volatile and less suitable for portable applications. EEPROMis non-volatile, but writing is slow, and requires a high write voltage, making reconfiguration on-the-fly impossible.  
  Almost magic… A single cell of FRAM acts as both ROM and RAM simultaneously doubling capacity by using a four-level sensing scheme. The RAM data is lost at power-down, the ROM data is not.
The paper proposes an architecture where an MPU core and a controllable logic block share a single large bank of FRAM, making it particularly suitable for setting-up custom logic blocks, DSP processing elements for instance, under MPUcontrol.
In addition, it proposes that the FRAMis operated in two modes to save power:in ROM mode the FRAMoperates conventionally, but where volatility is permissible the memory is written with lower voltages, introducing a ‘RAM’ mode.
Lower write voltages do not drive the ferroelectric material so far up its hysteresis curve, only sufficiently high to hold its state while power is maintained.
The same low voltage is able to read the FRAMin both ROMand RAM modes.
Remarkably, the authors go on to suggest that a single cell can be used to store both ROMand RAM data simultaneously where the level changes due to the RAM-write are insufficient to erase the ROM-written data and a four-level two-bit cell can operated.
Involved in the research were:Matsushita Electronics, Osaka; Osaka University; Panasonic Technologies, Cupertino, California and Stanford University.


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