Alchemy to build ‘formidable' processor with MIPS32 instruction set at the core

Alchemy to build ‘formidable’ processor with MIPS32 instruction set at the coreRichard Ball
Turning base metals into gold is the alchemist’s dream, but will Cadence’s Alchemy design team do the same with the MIPS32 instruction set?
Alchemy announced its intention to design MIPS processors last week, a major coup for MIPS Technologies. And the general consensus seems to indicate Alchemy will succeed in creating a formidable processor.
And why not? Alchemy is the same team that developed the StrongARM for Digital Semiconductor.
“The team is unique with their track record in high performance, low power design,” said Cadence’s senior v-p, Shane Robison.
Indeed StrongARM, now owned by Intel, is still setting the benchmark in terms of performance per Watt. The 233MHz SA-110 device, for example, typically dissipates 360mW, giving 750Mips per Watt.
Certain MIPS based devices are coming close, such as NEC’s VR4100 series, with around 500Mips/W. At the forthcoming Embedded Processor Forum in the US, Hitachi will announce its SH-4 that claims to break the 1,000Mips/W barrier.
Alchemy can probably be expected to do at least as well, if not better. It has licensed the MIPS32 instruction set, which means the group can do pretty much whatever it wants with the core. MIPS has already designed a core around the architecture, calling it Jade (see diagram).
But Alchemy can be expected to beat Jade on performance and power consumption, at the expense of not having a synthesisable version.
A core with several hundred Mips performance could easily fit within the 0.5W power ceiling Alchemy has set itself.
Any processor designed by Alchemy will be compatible with the R3000 and R4000 class of MIPS devices, making it attractive to companies developing a variety of systems.

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