Analog snaps at TI's heels with Sharc II

Analog snaps at TI’s heels with Sharc IIRoy Rubenstein Analog Devices has fired a shot across the bows of Texas Instruments (TI) with the unveiling of its second generation 32-bit Sharc DSP family. Of the leading DSPvendors, it is Analog and TI that are the key players in the 32-bit DSP market-place. Indeed during the recent announcement regarding Motorola’s and Lucent’s co-development of DSP cores, Motorola’s Fred Shlapak confirmed that the two would not be addressing the 32-bit DSP market: “The 32-bit space is not a significant part [of the market-place] – not yet.” This contrasts sharply with Analog Devices’ view. Gerald McGuire, Analog’s manager for 32-bit DSPs, describes the segment as the fastest growing one within DSP, expected to reach $1.3bn by 2001, and one that the company wants “to dominate”. Samples of the ADSP-21160, Analog’s first-announced next generation Sharc, are expected in the third quarter of the year. This coincides with samples of Texas Instruments own 32-bit DSP, the TMS320C6701. Both the Sharc and the C6701 are targeted at applications such as medical imaging, pattern recognition, defence, cellular basestations and voice mail servers. However, whereas the very long instruction word architecture C6701 represents a break with previous TI 32-bit DSP families – the C3x and C4x, Analog Devices is claiming its stake by building on the the success of its existing Sharc. Retaining code compatibility, points out McGuire, “allows users to leverage a wealth of algorithms and tools” . Analog Devices most powerful current Sharc is the 60MHz ADSP-21065L, which has a peak processing rating of 180 million floating point operations per second (MFlops). The 21065L has 544kbit of on-chip RAM, deliberately small to achieve its $10 cost (in volume). The current highest density on-chip memory Sharc has 4Mbit of SRAM. For its second generation Sharcs, Analog Devices has introduced several architectural enhancements. The most significant is the inclusion of a second computational unit. Each unit comprises a multiplier, barrel shifter, two accumulators and a register file. Having two such units turns the Sharc into a dual multiplier-accumulator (MAC)architecture; or as Analog describes it, a single-instruction, multiple-data (SIMD)architecture. When executing a fast Fourier transform, the Sharc’s two units execute up to six operations every clock cycle. According to McGuire, the two units accelerate mainstream algorithms by an average factor of 1.85. Clocked at 100MHz, the 0.25?m process 21160 has a peak processing rating of 600MFlop/s. TI’s 167MHz C6701 has a peak processing performance of 1GFlop/s. Other Sharc enhancements include a five-fold increase in the data transfer performance of the 64-bit wide general host port’s, to achieve 800Mbyte/s. The six link ports have also been enhanced, from 40 to 100Mbyte/s. Via the link ports, each Sharc can be interfaced to up to six others for DSP multiprocessing applications. In contrast, TI’s latest floating point architecture, the C6701, does not have ports. According to McGuire, the ADSP-21160 will be in volume production by the second quarter of next year. At the family’s high-end, a 200MHz, 1.2GFlop/s peak performance Sharc will be introduced.
Meanwhile, Analog Devices’ designers are developing a third generation superscalar Sharc. “If you look forward 18-months from now, there will be two families: one based on this one [second generation Sharcs], and a very high performance, low cost one,” said McGuire.


Leave a Reply

Your email address will not be published. Required fields are marked *

*