Changing technology provides new challenge for design tools

Changing technology provides new challenge for design toolsEDA might be relatively small in terms of revenue but, as Richard Ball explains, it is critical to the multibillion dollar semiconductor industry and hence the trillion dollar electronics industry
Like it or not, EDA tools are critical to modern chip design. Whatever anyone says, you simply cannot design a decent sized Asic without modern EDA tools. Or maybe you could, but not without being several years late to market.
So although EDA is a relatively small industry in terms of revenue – under $3bn last year – it is absolutely critical to the $134bn semiconductor industry and hence the trillion dollar electronics industry.
Aart deGeus, chairman and CEOof Synopsys, thinks EDA has an important part to play.”There is an enormous amount of change upon us,” he says. “The semiconductor industry is going to be shaken up considerably. We will be at the heart of leading this change.”
Apart from smaller processes, Moore’s Law and technical advances like copper interconnect, these changes in the semiconductor industry are being led by the move towards intellectual property (IP) and systems on a chip (SoC).
“We’re entering a very interesting time,” says Bryan Lewis, Asic analyst at market research firm Dataquest. “We now have the capacity to put an entire system on a chip. This will change the dynamics of the industry as when the first CPU was introduced.”
Within three years, the number of SoC Asics will exceed the number of non-SoC devices. Products using these devices include mobile phones, set-top boxes, games, and PCs.
Prakesh Bhalerao, CEOof synthesis firm Ambit, says: “The whole thing revolves around silicon. We’re an ancillary industry to silicon. As silicon changes, EDA must move with it.”
Those companies that embrace SoC will survive, ready to face the next industry crisis. “The reason companies like Ericsson are successful is that they’ve been doing this for four years,” says Bernd Braune, senior vice-president at Mentor Graphics.
Unfortunately, these changes mean existing EDA tools will at best be stretched and possibly be unable to meet the challenge.
“The number of gates available for the same price has multiplied many times,” says Bhalerao. “There is so much capacity coming on line, this will force a design methodology change.”
Indeed, we are seeing this with a new generation of tools, particularly for verifying designs.
EDA companies are now selling tools for formal verification, static timing analysis, cycle based simulation and hardware and software co-design, not just for the few high end designs, but for many of the mainstream Asic projects.
The main problem for the past couple of years has been verifying the designs. The constant simulation needed throughout the design cycle is a sore tax on resources and time. Although tools like formal verification promise much, every semiconductor improvement makes the EDA problem worse. To prove a point, the latest hitch in Intel’s 64-bit Merced processor – a delay of six months – is due to verification problems.
“Semiconductor companies are providing increasing numbers of gates, so the tools will always be stretched,” says de Geus. “There will always be a gap between what the engineer can design and what can be produced. Verification will be playing catch-up for the foreseeable future.”
So while SoC helps solve the design problem and reduce component costs, it makes verification even harder than it is now.
Jack Harding, president and CEOof Cadence, agrees:”Verification as a problem is not going to go away. A third to a half of our R&D goes to some form of verification.”
The increasing use of IP is critical to the continued success of the semiconductor industry. As Synopsys’ de Geus says:”It’s clear that no very large chips will be done without IP.”
Therefore, to help chip designers some EDA firms aim to provide the blocks of IP needed in SoC devices.
Mentor Graphics is leading the charge with its Inventra business unit. Inventra develops its own IP and acts as a publisher for other firms’ IP. Project Alba in Scotland will also act as an IP repository
Synopsys has approached the problem from another direction. It has forged links with the silicon suppliers themselves – the Asic houses.
Over the past few years, the company has developed a library of physical layouts for common logic gates and simple circuits. This is called cell based array (CBA). A circuit designed using CBA can be made at any Asic house licensing the technology, of which there are around 30.
To improve their chances of making money, Mentor and Synopsys have teamed up to ensure that Mentor IP is manufacturable on Synopsys CBA. “We decided to take the Inventra cores, map them onto CBA and tape them out to check they work,” says de Geus.
The two companies are also licensing their tools to improve the design flow. Mentor’s Braune says:”Tool interoperability will change the industry and will help startups.”
Another issue is the number of EDA tools and the way they are used. Today, the average Asic size is around 250,000 gates. In just five years, this figure will increase to at least two million gates.
The complexity of the circuits means designers will require multiple tools to synthesise, simulate and perform all the other design tasks.
“The number of copies of EDA tools is going to explode,” says Bhalerao. “We used to have several engineers per licence. Now we’re moving to several licences per engineer.”
Ambit’s latest release of Buildgates, its synthesis tool, can be used in multiples to split the synthesis task across several processors.
Model Technology, which sells simulators for VHDL and Verilog designs, agrees with this assessment. The company has just done its biggest deal, selling 3,000 simulators to a company for use by just 300 designers.

Leave a Reply

Your email address will not be published. Required fields are marked *