Chrysalis tools aid IC design

Chrysalis tools aid IC designRichard Ball
Chrysalis, the leading formal verification company, has announced a new set of tools, targeted at solving specific IC design problems.
Called formal design rule checkers, the tools are designed to take some of the verification load at the register transfer level of chip design.
“Formal design rule checkers verify logic functions that are difficult or impossible to do in simulation,” said Tom Rathje, v-p of product development at Chrysalis.
Four areas have been targeted by Chrysalis; clock domain checking, one-hot checker, reset checker and a scan checker.
The clock domain checker, for example, proves that a system with multiple clocks will synchronise correctly. Designers of multi-clock systems, often found in telecom and network applications, today use a slow, error prone process to trace signals between clock domains.

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