# Clock dithering technique tackles chip interference

Clock dithering technique tackles chip interferenceRichrd Ball    The tendency for high speed equipment such as handheld PCs to emit more electromagnetic interference (EMI) has been addressed by researchers at Korea’s Seoul National University. A paper at ISSCC has shown a clock dithering technique that spreads the frequency spectra of clock and data signals, and hence reduces their peaks. The work is aimed at devices such as notebook computers which have high clock and data speeds, but cannot afford the weight and cost of too much shielding material. Seoul University’s method is called spread spectrum phase modulation (SSPM). The clock signal is dithered such that its phase varies over a number of clock cycles. A fast Fourier transform analysis showed that different phase changes gave a variety of reductions in EMI. EMI peaks should be reduced by 5, 13, 6 and 3dB as phase is changed by 90?, 180?, 270? and 360? respectively.

Clock dithering technique tackles chip interferenceRichrd Ball

The tendency for high speed equipment such as handheld PCs to emit more electromagnetic interference (EMI) has been addressed by researchers at Korea’s Seoul National University. A paper at ISSCC has shown a clock dithering technique that spreads the frequency spectra of clock and data signals, and hence reduces their peaks.
The work is aimed at devices such as notebook computers which have high clock and data speeds, but cannot afford the weight and cost of too much shielding material.
Seoul University’s method is called spread spectrum phase modulation (SSPM). The clock signal is dithered such that its phase varies over a number of clock cycles.
A fast Fourier transform analysis showed that different phase changes gave a variety of reductions in EMI. EMI peaks should be reduced by 5, 13, 6 and 3dB as phase is changed by 90?, 180?, 270? and 360? respectively.

Therefore, for best results, the system was designed to vary the phase of the clock between 0 and -180?. Each consecutive edge changes the phase of the clock by 3.3 per cent of a clock period. A phase of -180? is reached in about 16 clock cycles. Then the process reverses and the phase is brought back to 0?.
Thus periods when the clock is either at 0? or -180? are interspersed with periods when the clock is running faster or slower.
The researchers fabricated a delay locked loop (DLL) using 0.35?m CMOS. The core size is 0.6 x 0.4mm and it consumes 45mW at 3V.
The diagram shows the radiated spectra from this prototype system running with a fundamental frequency of 82MHz. Current driven by clock and data drivers was passed through a metre of unshielded ribbon cable.
Measurements were based on CISPR16-1, an international standard for measuring radio interference. The reduction in EMI is around 13dB at the fundamental and third harmonic.
Measurements of conducted spectra showed a similar result; spectral energies are spread and peaks of the fundamental and harmonics were reduced by 13dB.