Columbus explores interconnect delays

Columbus explores interconnect delaysRichard Ball  
 
The move towards smaller semiconductor manufacturing processes is causing problems for chip designers. Predicting the timing of the chip is becoming more difficult as interconnect, the metal connecting transistors and gates, start to cause major delays.
Founded last year, Frequency Technology has come up with a solution to part of the problem. It has tools for measuring interconnect delays.
“As people go below 0.25?m, the interconnect takes over the performance of the chip,” said Michel Courtoy, v-p of marketing. How does it work?
Columbus works from a three dimensional library of resistor/capacitor elements that represent the semiconductor process being used by the chip designer. For each layer of metal in the process there are about 10,000 elements in the library.
When a chip design is being analysed, the net being tested is compared to the elements in the library. On a typical workstation, Courtoy said the software can analyse half a millimetre of interconnect a second.
So the delay along a particular net can be calculated in a few seconds or minutes for long nets like clocks. Because the tool works on a net at a time, the workstation’s memory requirement is reduced.  
 
Until now, the delays through a chip and the overall timing have been largely determined by the transistors themselves. So software for accurately measuring delays, called parasitic extraction tools, has focused on the transistors and gates.
“But at 0.18?m, 80 per cent of the delays can be due to interconnect,” said Courtoy.
Therefore, Frequency Technology has developed Columbus, a parasitic extraction tool which determines the part of the delays due to interconnect.
Version two of the tool has just been released which fits into existing physical design flows from Avant!, Cadence and Mentor. It offers accuracy of five per cent, Courtoy claimed.
A new tool announced this week is Cartier, a subset of Columbus designed for clock tree analysis.
The clock tree of a high speed Asic or microprocessor is almost always the most complex net on the chip. It also has the tightest timing requirements. “People are designing chips at several hundred megahertz. Clock cycles can be two nanoseconds. With ten per cent clock skew, this gives just 200ps to play with,” Courtoy said.
If the clock tree can’t be modelled, the overall performance of the whole chip ends up as a lottery.
“People go in expecting a chip to run at 400MHz and get something significantly less than that,” said Courtoy.
Cartier is designed to work with automatic clock tree generation tools from Avant! and Cadence.


Leave a Reply

Your email address will not be published. Required fields are marked *

*