DAC sees ‘less painful process for designers'

DAC sees ‘less painful process for designers’Richard Ball
Announcements of industry wide significance at the Design Automation Conference this year were those concerning the licensing of design constraints from Cadence and Synopsys.
These announcements promise a less painful process for chip designers.
Design constraints are used to drive the EDA tools for synthesis, timing analysis and place and route. So synthesis constraints tell the tool whether to optimise for speed, area or power.
However, these constraints are often proprietary, so the same file cannot be used by different tools in the design flow, for example, Synopsys synthesis with Cadence layout tools. This results in needless and wasteful iterations of the design process.
If the synthesis constraints could also be used for verification and place and route, then timing, area or power limits would be met more easily, reducing the number of re-synthesis loops.
Thus Synopsys’ decision to make the Liberty design constraints available under licence was widely welcomed, even with a $95,000 price tag.
Cadence’s constraint formats, on the other hand, focus more at the physical level of a design. They allow ‘back end’ design tools, such as floorplanning, place and route, analysis and extraction tools, to communicate and share data.
The library exchange format (LEF) and data exchange format (DEF) will be available from next year. Cost of licensing the formats is not yet known, but Cadence promises them to be either free or very low cost.
Also of significance at DAC was a demonstration of the Asic council’s open library application programming interface (OLA).
The OLA aims to provide a single library format for all Asic vendors and EDA tools. Today, Asic vendors are developing a different library for each EDA tool.
Unfortunately, of the two formats chosen by the Asic council for functionality and timing, the former is not compatible with Synopsys’ Liberty format. On the plus side, Cadence’s LEF and DEF support the OLA.
The Asic council includes IBM, LSI Logic, Lucent, NEC, TI and VLSITechnology.


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