Designers in ARC link up

Designers in ARC link upRichard Ball
ARC Cores and Mentor Graphics have teamed up to provide virtual prototyping for designers using ARC’s 32-bit Risc processor core.
The system uses Mentor’s Celaro hardware emulator. ARC has made a pre-verified model of its core which allows users to develop and verify application software before the final Asic is manufactured.
Other parts of the Asic are emulated in the Celaro system to make up a prototype of the whole chip.
Mentor expects the core to run at around 1MHz in the emulator – much faster than simulation. However, emulators can cost millions of pounds – so why use one?
“When you’re designing a system-on-a-chip, the costs of getting it wrong are tremendous,” said Mentor’s Guy McBride.
For applications such as third generation mobile phones, getting to market quickly is all important.

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