EDA firms champion Cadence in drive to simplify chip design

EDA firms champion Cadence in drive to simplify chip designRichard Ball The electronic design automation (EDA) community has taken another step forward in its drive to simplify chip design by standardising on design constraints from Cadence.
Open Verilog International (OVI) and the Virtual Socket Interface (VSI) Alliance collaborated in choosing the Cadence constraints. This will make it easier for different EDA companies to make their tools work in an integrated design flow.
Constraints on the design, such as timing, area or power, will be able to be passed between different companies’ tools. This will increase productivity and promote design reuse. The OVI standard
The OVI standard is also expected to be adopted by the system level design language (SLDL) initiative. The system level, early on in the design process, is the point at which designers make many of the most important trade-offs in their design, such as the split between hardware and software.
They can constrain timing, power, signal integrity and size. The system level is where all these constraints are most easily evaluated against each other, said Cadence’s Mark Hahn. If the SLDL uses the same standard, then the constraints decided upon will be passed through the entire chip design process in the same format, improving the quality of design.
However, the use of Cadence’s constraints may take a while to become the norm as the majority of designs carried out today use constraints from Synopsys.
It may seem an obvious question, but why didn’t the OVI and VSIAlliance choose to use Synopsys constraints?
The Synopsys design constraint is used in almost every design out there, said Karen Bartleson, standards programme manager at Synopsys. But, she pointed out,we don’t give it away for free.
Mark Hahn, chairman of the OVI’s design constraints working group (DC-WG), told Electronics Weekly:The DC-WG discussed using the Synopsys constraints with Synopsys, but it wanted to keep control. The OVI wants truly open standards.
To be fair to Synopsys, it’s not just about licensing and money. If you donate them [the constraints] to a committee, they take many years to come out as a standard, claimed Bartleson. We need these design constraints today.
Hahn disagreed on the timing:The OVI standard will be available by the end of the year. We’ve got a pretty solid footing at this point.
Whatever the timing, it is probable that chip designers will eventually shift to using the OVI/VSI standard.
Over time there’ll be a migration away from proprietary standards and more towards open standards, said Hahn.
In the meantime, Cadence and Synopsys are engaged in the Spine ‘99 initiative. This allows constraints to be passed between Synopsys’ synthesis tools and Cadence’s IC layout tools.
Synopsys design constraints are a key piece of the Spine today, said Bartleson. Spine ‘99 is an immediate solution to the interoperability problem.


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