EDA firms speed up 3G design

EDA firms speed up 3G designWith the time available to develop third generation mobile chipsets constantly being eroded, EDA firms are under pressure to help quicken the design process. Richard Ball reports
Third generation mobile phones promise many enhanced services compared with today’s GSM phones. But the time available to develop the complex chipsets is constantly being eroded. Chipset designers and manufacturers are looking to electronic design automation (EDA) firms to speed the design process.
EDA firms are addressing these needs for faster development times with toolkits and models aimed specifically at the signal processing algorithms in wideband CDMA – the foundation to third generation (3G) mobile phone services.
At the GSM World Congress last month, Synopsys announced a set of design kits and services for 3G mobiles. These are based around its COSSAP design flow.
In January, design automation firms Frontier Design and HP EEsof teamed up to provide a design and development flow for 3G mobile phone chipsets.
And Cadence has a CDMA toolkit as part of the software from its Alta Group. It also has a design service provided by Symbionics, the Cambridge firm it bought this time last year.
Synopsys’ wideband-CDMA toolkit includes models for the complex algorithmic building blocks and a set of configurations that represent different aspects of the W-CDMA system. These centre on the UMTS and ARIB standards.
“Synopsys supplies a set of reference schematics and C models representing key components in a 3G module for baseband processing,” said Martin Phipps, systems specialist at Synopsys.
Models and configurations cover channel encoding and decoding, rate matching, orthogonal variable-length code generation, channel estimation, RAKE receivers, accurate propagation channels and receiver front end models.
“We provide the starting blocks – an end to end reference design,” said Phipps. This reference design represents the ideal system. As the customer adds in the actual circuits for the blocks, the performance of those blocks can be compared to the reference design.
Another aspect of the Synopsys tool is its compliance testing capability. “This is something we developed in conjunction with Lucent Technologies for GSM,” said Phipps.
Some 350 different simulations can be performed on the software under test. These include simulations of the physical compliance tests that will be carried out on the final handsets and basestations.
Such testing will increase confidence in the design before it is committed to hardware.
The third part of the COSSAP toolchain is the ability to link into hardware verification tools such as emulators and FPGA prototyping.
Some next generation mobiles will include video links, which require video compression. So the COSSAP tool also provides models and configurations for MPEG-2 video codecs. These include the discrete cosine transform and its inverse, motion compensation and control functions.
The link up between Frontier Design and Hewlett-Packard’s EEsof group aims to provide a complete design and development flow for W-CDMA mobiles.
“We are HP’s preferred design house, because our methodology is suitable for this area and is complementary to HP EEsof,” said Marc van Canneyt, Frontier’s director of business development. “The major objective is for Frontier and HPto offer a complete solution.”
HP EEsof has spent several years developing a capability for high level simulation and design of wireless systems. “They have a good reputation in the market,” said Canneyt.
It already has models available for protocols including wideband-CDMA, CDMA2000 and GSM. As soon as standards for 3G phones are ratified, the company will be able to help telecoms firms design their systems.
Frontier, on the other hand, has tools for taking the high level description and creating signal processing chips for handsets and basestations.
“We have been addressing a different part of the design flow than other companies,” said Canneyt.
Frontier has looked at the problem of moving from an algorithmic description of the system to the architectural level. In simpler terms this, in most cases, means converting from C-code to register transfer level (RTL) code, normally in the form of a hardware description language (HDL).
This process has traditionally been done by hand, re-coding C to the HDL. However, errors can be introduced and HDLs typically require three times the number of lines code than C, making this a laborious task.
Frontier has developed an automatic translation tool called A|RT. “At this time this is unique. This is the only EDA tool that starts design from C-code,” Canneyt said.
Such a tool is very helpful in the wireless world where developing protocols is critical to the success of the system.
Another advantage of a quick translation from algorithm to RTL is that different algorithms can be tested in the system architecture. If the design is not right, the C-code can be modified and quickly updated back to the HDL.
EDA market leader Cadence is also involved with 3G design, both through its tools and Symbionics, its subsidiary which specialises in designing wireless systems.
Cadence says modelling and simulating the critical algorithms can alleviate many of the problems associated with mobile phones such as interference, multipath fading and audio distortion.
The company’s CDMA Toolkit for accomplishing this uses a tool called signal processing worksystem, or SPW. This is a system level tool for testing algorithms and exploring architectural trade-offs between hardware and software.
An algorithm can often be implemented in either software or hardware. In the former, it is code running on some form of processor. In the latter, dedicated registers and logic carry out the algorithm’s function.
After the design is captured at the algorithmic level, simulation using SPW can determine effects of the acoustic and radio parts of the system.
Like other tools, the customer’s own design for the blocks of the system are substituted in place of the models, eventually building a complete system. The design is compiled from this high level to the RTL using Visual Architect. Conventional hardware design and verification can then go ahead.
Cadence is in the process of adapting its CDMA toolkit to the latest ETSIspecifications for 3G mobiles.

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