Embedded Processor Forum – New set of benchmarks released for embedded processors

Embedded Processor Forum – New set of benchmarks released for embedded processorsRichard Ball
At the Embedded Processor Forum, a new set of benchmarks for embedded chips were unveiled, aimed at displacing Dhrystone Mips, arguably the most reviled of all benchmarks.
EDN magazine’s Embedded Microprocessor Benchmark Consortium (EEMBC, pronounced ‘embassy’) has spent two years developing the benchmarks which use actual snippets of application code to test processors in more realistic conditions.
Ten of EEMBC’s 28 member companies participated, including Analog Devices, ARM, Hitachi, IDT, Motorola, QED and Toshiba.
EEMBC’s benchmarks are split into five application sectors; automotive/industrial, consumer, networking, office automation and telecoms.
At the Forum, the most complete set of results came from the automotive/industrial sector. Five processors, from AMD, ARM, Infineon, Motorola and NEC were tested using 16 different code fragments.
On these, AMD’s K6-2 came highest, but then it runs at 450MHz and isn’t really intended for this application.
Of the rest, ARM’s 920T showed a clean pair of heels. After the results are normalised to 1MHz, it scored 2,741 running CAN-bus code compared with 1,835 for Infineon’s C167, 2,622 for Motorola’s PowerPC555 and 1,429 for NEC’s V832.
Similar results were obtained running code such as angle to time, pulse width modulation and an FIR filter.
As time goes by more processor results will be published on the organisation’s Website: www.eembc.org What’s wrong with Mips?
What’s wrong with Mips?Dhrystone Mips represent how much faster a processor is compared with a VAX 11/780 (it has a Mips rating of one). But for most micros, whether it’s eight, 16 or 32-bit, the Mips rating closely approximates the clock speed. Furthermore, it doesn’t care about the intended application. The difference in performance between transferring data and performing a complex fast Fourier transform is going to be dramatic on most devices. Mips also takes no account of the improvements to be gained by tweaking source code or using a better compiler. Because the Mips’ code is small, it often cannot test memory beyond the processor’s cache.

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