Embedded Solutions plays Handel to ease design headaches

Embedded Solutions plays Handel to ease design headachesA hardware compiler developed at Oxford University coupled with a hardware module incorporating a DSP and FPGA is about to set the design world alight. Roy Rubenstein looks at the technology
Tell an engineer that you can more than double the performance of their DSP and you will at least have their attention. Inform them that it will involve adding an FPGA to the DSP and the likely response will be one of disappointment. After all, designers are well aware of the benefits of producing fixed-function logic to implement a design.
The difficulty, and hence the reason for the disappointment, is that mapping a design onto an FPGA requires greater engineering effort than programming a general purpose processor.
This is something that Wokingham-based Embedded Solutions, with the launch of the Handel-C hardware compiler developed at Oxford University, hopes to change.
Through a value-added reseller agreement, image processing firm Quintek is offering designers the Handel-C compiler coupled with a hardware module incorporating a DSP and FPGA. The hardware, the APAC509 Sharcpac from Alex Computer Systems, comprises an Analog Devices’ floating point ADSP-21062 Sharc DSP and a Xilinx XC4013E FPGA.
The combination of the APAC509 hardware and the Handel-C compiler has already enabled a software engineer, with no knowledge of FPGAs, to develop a 3D graphics application. The resulting 3D solid renderer runs at more than twice the speed of its execution on the DSP alone.
According to Quintek’s managing director, Dr Patrick Mills, the APAC509 module is most commonly used for I/O purposes in DSP systems. Since the FPGA is connected to a 100-pin parallel port, it can easily implement the required interface logic.
However, the DSP and FPGA can be used for more ambitious applications, tackling problems that previously were intractable using just the DSP. “Subtracting two video frames in real-time to look for differences wasn’t possible before with just the DSP; with the two it’s not a problem,” said Mills.
Implementing the design on the APAC509 involves writing the application in C and running it first on the DSP. An optimiser is used to fine tune the algorithm’s inner loops. These inner loops are the prime candidates – being the most intensive tasks – for acceleration on the FPGA. Schematic capture or a hardware description language such as VHDL is then used to transform the loops for implementation in logic.
“It is important to acquire a gut feeling for just how much you can put on an FPGA,” said Mills. Implementing a multiplier requires 30 configurable logic blocks (CLBs) on the FPGA, while the Xilinx part has around 700 CLBs in total.
“The tools by Xilinx are all wonderful but nevertheless they are hardware based ones,” said Mills, on the issue of mapping the task onto the FPGA. “What you want, is to be able to work in a language like C, to work in a language software engineers expect.”
This is the key benefit that the Handel-C hardware compiler brings. It allows an engineer to design the hardware not at a gate level but by writing software. The engineer develops the design using a C-like language which is then processed by the hardware compiler. It also ensures that the routeing on the programmable logic device meets the desired timing constraints.
Handel-C also reduces the debug time compared to using VHDL. “Creating a new design version takes several minutes instead of hours,” said Mills.
  Atmel pushes programmable limit with AVR
Atmel has continued in its bid to fill the gap in the embedded microprocessor market that lies between the 8051 and low power ARM Thumb with its own AVR Risc microcontroller chips, writes Richard Wilson.
Twelve months after the launch of the first 8-bit AVR chip, the company has introduced the next variant of the family, called the megaAVR, which incorporates more in-system programmable flash and EEPROM memory.
There are also new peripherals, such as 10-bit A/D conversion, but the real message is in-system programmable memory, 128kbytes of it in the largest chip, which is important for a key application for AVR – pattern recognition.
“The real advantage of this device,” says Jim Panfill, director of marketing for microcontrollers at Atmel. “the flash/EEPROM is in-system prog rammable down to 2.7V.”
To support the level of memory, 128kbytes in the ATmega103 and the 64kbytes in the ATmega603 devices, without seeing the die size expand unacceptably, Atmel has ported its AVR core onto the memory process in order to optimise die size. “70 to 80 per cent of the die is memory,” adds Panfill.
The AVR core is unchanged. There are 120 instructions and two-stage pipelining in the core is limited to pre-fetch, where the next instruction is accessed from the program flash memory while the last is executing. This allows most instructions to execute in a single clock cycle. With maximum clock rates of between 16 and 20MHz, the cores can easily approach 16 to 20Mips performance. Added to this 8-bit microprocessor core, in addition to the 128 or 64kbytes of flash memory, is 4kbytes of EEPROM data memory and 4kbytes of SRAM.
New peripherals include a 10-bit, 8-channel A/D converter, a full-duplex UART, watchdog timer and real-time clock. According to Panfill, the next devices planned for the megaAVR family will double the on-chip memory to 2Mbit at the top end and there will also be a device with 32kbytes of flash.

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