Fast FPGAs threaten CPLD territory

Fast FPGAs threaten CPLD territoryRichard Ball Actel’s new SX field programmable gate arrays combine the attributes of both CPLDs and FPGAs claims the company due, it says, to its architecture and use of antifuses. FPGAs tend to be too slow when used to implement combinatorial logic functions like address decoders. CPLDs thrive in such applications, but lack the register structure and gate count to swallow large logic blocks. With a fast input pin to output pin delay of 6.6ns, the SX family is capable of taking on address decoding and other tasks normally reserved for CPLDs. At least part of the performance increase comes from reducing its die sizes. Moving from 0.45?m to 0.35?m processing has contributed, but much of the gain comes from moving the antifuses away from the silicon surface and up to between metal layers two and three. This has removed the need for tracking lanes in the silicon and allowed logic blocks to be packed tightly. The logic blocks are arranged on the die like an Asic, described by Actel as a ‘sea of modules’. Two types of cell, one register based and one combinatorial, are available. This regular construction and the availability of some 4,000 functions from a cell make the architecture synthesis friendly. Very fast interconnect between adjacent cells of 0.1ns, and fast connections of 0.4ns between groups of neighbouring cells, allow quick address decoding. Internally a 25-bit wide decode takes 2ns. The regular structure also lends the devices to the datapath functions best implemented in FPGAs. The clock-to-out speed is just 4ns. Maximum clock rates are 320MHz. Actel says the chips can implement a full speed 66MHz PCI-bus controller. The first device, the 16,000 gate A54SX16, could fit in functions currently served by a 5,000 gate FPGA and five 32-macrocell CPLDs.


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