Five-fold resistance cut for high-voltage FETs

Five-fold resistance cut for high-voltage FETsSteve Bush
Siemens has cut the on-resistance of high voltage power FETs, at a stroke rejuvenating a technological area which has been stagnant for years.
Dissipation due to device on-resistance dominates the power loss of FETs. In low voltage devices with sub-60V breakdown, there has been plenty of innovation such that device RDSon is often dominated by the package lead resistance rather than the chip inside.
The same cannot be said for high voltage power FETs, particularly those for off-line operation which need to withstand 600V. During the time that low voltage devices have seen a ten-fold improvement, 600V devices have lost only 30 per cent of their on-resistance.
Siemens claims that the best 600V FETs from its competitors achieve 18Ohm/mm2 of chip area, while CoolMos – as its new technology is called – will deliver 3.5Ohm/mm2. In packaged terms, this drops the on-resistance of a 600V TO220 device from 800mOhm to 190mOhm.
The up-shot of these improvements, says Siemens, is that power supplies of 3 to 4kW can now be handled by four TO220 packages, rather than TO264 packs or hybrid modules.
Developments like CoolMos are unlikely to change the dominance of IGBTs (high voltage insulated gate bipolar transistors) in multi-kW applications – industrial motor driver for instance. This is because IGBTs continue to have lower losses than any type of high voltage power FET. But IGBTs are slow; few operate above 50kHz, whereas power FETs will work at 1MHz.
This gives high-voltage power FETs a noteworthy niche, where high frequency operation reduces the size of associated magnetics. Application for high voltage power FETs include switch-mode supplies, uninterruptible power supplies, induction heaters and welding equipment. Reducing on-resistance by a factor of five, as CoolMos is claimed to do, will reduce the resulting equipment size and may open up higher power, high frequency applications which have been too expensive using more conventional power FETs.
CoolMos will be launched in volume later this year. Voltage in power FETs is blocked by the epitaxial N-type silicon layer in which the FET is constructed. Increasing voltage capability requires raising the thickness of the epi-layer and reducing its doping concentration. These measures also increase on-resistance, causing it to rise with the square of blocking voltage.
With CoolMos – also called SIP5 – Siemens has developed a structure which effectively increases doping levels when the device is on and reduces them when it is off. This reduces on resistance while increasing off-state blocking voltage.
For a given thickness of epi-layer, Siemens increases blocking voltage by cutting doping compared with conventional FETs. This would normally result in an unacceptably high on-resistance. To counter this, trench technology is used to bury a highly doped N-type column under the gate of the device where current flows when the device is on. Doping this at five times the level used in a conventional FET drops on-resistance by a corresponding factor.
This on its own is not enough. Although the column reduces on-resistance, it offers an easy path for carriers from the source contact during break down and therefore lowers blocking voltage.
To increase blocking voltage again, P-type material is trenched around the column. This material has the same doping concentration as the column.
In the off state, carriers from the N-column and the P-trenches migrate into each other’s areas, creating a depletion region. By carefully balancing the doping, both the trenches and the column can be made to ‘disappear’, effectively becoming weakly doped N-type material like the rest of the epi-layer. This action pushes the blocking capability back up to that of the surrounding epi-layer.
The P-type trenches play no part in the operation when the device is on.
Siemens is using a stripe structure in the devices, so that the two trenches and column are long structures, going into the page in the diagram.

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