IBM's copper 'ready to roll'

IBM’s copper ‘ready to roll’
David Manners IBM Microelectronics has a copper interconnect on silicon on insulator (SOI) process available for prototyping which can draw gate lengths on silicon down to 0.11?m. “For the past couple of years our process technology has been very showy,” said Dr Lisa Su, project manager for CMOS Logic Technologies at IBM Microelectronics, pointing out that the 0.11?m features are drawn using a 248nm UV wavelength. At the moment, the process is available to customers only for prototyping, but, said Su “it is ready to roll”. Before volume production is available to OEMs, an Asic library for the process has to be readied. According to IBM, this is currently being prepared. IBM has used the process internally to make PowerPCs and Asics. It expects customers to use it for the IBM BlueLogic system-level chip offering and for Asics used in high-end servers. Using copper interconnects speeds up chips by 10 to 20 per cent compared to aluminium, says IBM, while using SOI wafers improves transistor performance by up to 35 per cent and offers up to a threefold reduction in power. Although SOI wafers cost three times the price of silicon wafers, according to Andre? Auberton-Herve?, president of SOI wafer suppliers SOITEC, the extra cost for finished silicon is only ten per cent, claims Su. IBM calls its copper/SOI process SA27E. “The reason SOI is so attractive is that it is an ideal transistor,” said Su. “The difficulties with it have been in getting good enough materials without defects. What has kept people away from SOI is that scaling has been going so fast that SOI couldn’t catch up. It could only be useful if SOI and silicon scaling were equivalent. Now SOI has caught up.”

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