ICL chip tool zaps bugs at early stage

ICL chip tool zaps bugs at early stageRichard Ball The design automation group at ICL in Manchester is to market SuperVISE, its internal chip development tool. The tool aims to remove more bugs and errors from a chip design at the early stages. It accomplishes this by forcing engineers to spend more time at the specification stage of a design and by starting verification at this stage. “The industry is driven by Moore’s Law, and we’re driven by the line that relates to Asics,” said Jim Heaton, business manager at ICL. Designers are falling behind in their ability to create chips required by electronics systems, Heaton said. Complexity of Asics grows by over 50 per cent a year, but productivity of designers cannot even make half of this, only increasing by 21 per cent a year. ICL used SuperVISE in the chipset design for its latest mainframe. The Trimetra project comprises seven chips of a million gates and five over half a million. After the chips were produced the operating system booted up first time. The number of bugs in the hardware was reduced from over 50 per million gates on the previous design to one per million. An independent trial has been carried out by Ericsson. “They did a methodology experiment that ran in parallel with a live project, developing a telecoms switch,” said Heaton. The SuperVISE team completed the design with a 25 per cent overall reduction in design time compared with Ericsson’s normal method. “Ericsson said getting to market 25 per cent earlier would generate enough revenue to pay for the whole development costs,” Heaton said. The development of SuperVISE started after the last mainframe design ended in 1992. Looking at the bugs that surfaced in the ECL-based chips, the team found that most were in the interfaces between the blocks of the design. Tools for solving the problem were unavailable, so ICL developed its own. Central to this was the specification of VHDL+, based on the industry standard language, but with a few extra keywords and constructs. VHDL+ is even more abstract than behavioural VHDL, and uses around a tenth of the lines of code. Because VHDL+ is used during the initial specification stage of a design, verification can start earlier, leading to removal of bugs and errors early in the design cycle. The earlier that problems are identified and sorted, the quicker the overall design takes, especially if no re-spins of Asics are needed.
Having chips that work first time also helps during the integration phase of a project. With ICL’s latest mainframes, Heaton said:”Integration time was 50 per cent of the previous design.” The team took a year from powering up silicon to delivering the system to customers.

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