ICL tool slashes design times

ICL tool slashes design times
Richard Ball A method of chip design that could cut design times by a quarter has been developed by ICL. The company is marketing SuperVISE, its in-house developed design tool, as a way of saving companies millions of pounds. The tool is used early on in a design and helps to weed out bugs and errors. Telecoms company Ericsson has tested the tool in parallel with its normal design methods. The team using SuperVISE shortened the design time by a quarter. “Ericsson said getting to market 25 per cent earlier would generate enough revenue to pay for the whole development costs,” said Jim Heaton, business manager at ICL. Heaton estimates that the industry would save $5bn if all electronics systems were designed using the tool. The ICL method uses an extension to the VHDL hardware description language called VHDL+. This is used to describe the system at an abstract level during the early design specification stage. See Technology


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