IEEE gives go-ahead to extend VHDL language

IEEE gives go-ahead to extend VHDL languageRichard Ball
Analogue and mixed signal extensions to the VHDL hardware description language have been approved by the IEEE. Informally, the language is called VHDL-AMS.
Officially designated as IEEE Standard 1076.1-1999, the extensions allow for the description and simulation of analogue and mixed signal blocks from the system level down to transistor level.
We designed VHDL-AMS with the needs and benefits of the model writer in mind, explained Ernst Christen, of the 1076.1 working group, and an engineer at Analogy. Rather than designing an analogue language first and then merging it with VHDL, our approach was to define a mixed-signal language that builds on the full power of VHDL. The result is a unified language environment, where analogue and digital modelling constructs complement each other. VHDL-AMS is a true top-down design language for mixed-signal system and IC design.
The approval of VHDL-AMS is a boost for Analogy, which is developing a new simulation strategy dubbed TheHDL.
VHDL-AMS, along with the other existing and emerging hardware description languages is a key component of our TheHDL vision for a language-independent, open simulation environment, said Doug Lundin, v-p of marketing at Analogy.
TheHDL will be a single kernel simulator that supports multiple hardware description languages, including VHDL, Verilog and MAST. Use of a single kernel means that the simulator will be more efficient at solving analogue and digital parts of the design.


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