Introducing the Siemens Carmel processor

Introducing the Siemens Carmel processorSteve Bush As described in last week’s EW (April 1), the architecture is based on the premise that a DSPspends 90 per cent of its time in small loops executing 10 per cent of its code, and that systems must maximise throughput whilst minimising programme memory size. Code inside inner loops is executed quickly using the whole width of the processor and instructions are allowed to be up to 144-bits long. Code outside these loops is in 24 or 48-bit word format to keep memory requirements down. The core is two-way superscalar and is capable of 15 basic operations in parallel. This parallelism and variable word-length structure means extra silicon area, but Dr Reinhard Rueckriem, director of Siemens’ DSP business points out: “When you are designing a system on a chip, reducing memory area more than makes up for using more area in the DSP core.” Clock speed is 120MHz (2.5V), leading to 120DSP Mips performance, or 1.8Bops peak with 15 parallel basic operations.
1mW/Mip is predicted at 2V when 0.25?m Carmel chips become available. 0.18 and 0.13?m versions are also planned.

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