I<sup>2</sup>C extended

I 2 C extendedRichard Ball
Philips Semiconductors has extended the I2C bus specification to work at data rates of up to 3.4Mbit/s.
The company has also developed a voltage level shifting technique for linking 5 and 3V chips without requiring extra discrete components.
“Already extensively used in microcontroller based products, it offers low cost and easy design-in,” said Theo Claasen, Philips’ chief technology officer. “Now, these enhancements offer real future proofing, with speeds well in excess of those in common use today.”  
  I 2 C AT A GLANCE Developed by Philips in 1980. Just two wires link all I2C devices together. Standard (S) mode runs at 100kbit/s. Fast (F) mode of 400kbit/s introduced in 1992. Licensed to more than 50 semiconductor companies.
The bus’s high speed (Hs) mode adds to the existing standard (S) and fast (F) modes. Existing devices can continue to use S and F modes through the use of a bridge.
This allows Hs-mode devices to communicate bi-directionally at the higher 3.4Mbit/s speed, while letting S and F mode devices run at their sub-Mbit/s rates.
Because the bridge blocks the high speed data from reaching the slower S and F mode devices, load and electromagnetic interference are reduced.
The bidirectional voltage level shifter allows, for example, Hs devices at 3V to work with S and F chips at 5V.
The address space, which gives each device on the bus its own number, has also been extended, from seven to ten bits. Thus 1,024 devices can co-exist on the same two wire bus.
Philips expects the Hs-mode will be used for high speed data transfer from devices such as memories, including serial RAM, EEPROM or flash. Other applications include data transfers to liquid crystal displays and between processors and analogue to digital interfaces (A/D and D/C converters and so on).


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