It's logical to be physical design

It’s logical to be physical designRichard Ball
A US start-up has unveiled a chip design tool that aims to ease the transition from logical to physical domains when designing deep sub-micron ICs.
The tool from Silicon Perspective Corp. (SPC) carries out placement of logic gates following synthesis. It separates the job of placement from the routing tool with the aim of reducing overall layout time.
Called First Encounter, the tool is able to partition the chip design, place blocks and cells and perform trial routing. It also carries out parasitic extraction, timing delay calculations and timing analysis.
The typical design flow would be to take a netlist and timing files from a synthesis tool and use SPC’s tool to produce an IC layout that only requires routing.
By separating the placement from the routing, the designer can decide earlier on whether a layout is going to work. Because designs normally need a number of iterations back to synthesis, overall design time is reduced, the firm said.
The company claims to have tested its tool on three projects. One of these, from Trident Microsystems, is a 0.25?m device using over a million gates of logic.
SPC is the second start-up company this month to announce tools that sit between synthesis and layout, aimed at improving quality of results and speeding up the back-end chip design process.
Two weeks ago Sapphire Design Automation launched its toolset that integrates electrical analysis, placement and circuit optimisation.
Sapphire’s FormIT tool carries out much the same tasks as SPC’s First Encounter. But Sapphire adds analysis of signal integrity and power through tools called NoiseIT and PowerIT.
Whatever their differences, both companies’ tools will go up against offerings from Synopsys and, in the near future, from Cadence.
Synopsys’ Chip Architect links Design Compiler, its synthesis tool, with placement. Cadence is expected to do the same with its Ambit synthesis tool.

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