LogicVision puts built-in test on digital and mixed Asics

LogicVision puts built-in test on digital and mixed AsicsRichard Wilson The ability of IC manufacturers and designers to use on-chip testing of products could be extended by what a Californian test software firm is calling embedded ATE. LogicVision’s approach for providing built-in test function on complex digital and mixed-signal Asics is to embed test interfaces and some high-speed test functions into the IC design using between 2,000 and 10,000 gates. The firm sells the intellectual property for the test cores along with design automation tools and test programs that will enable test functions such as at-speed test and diagnostics of random logic, embedded memories, mixed signal cores to be embedded into the device. There are also test functions for device interfaces such as I/O and memory. The technology makes use of existing design for test techniques such as 1149.1TAP and Boundary Scan but, according to LogicVision, extends the test capability. Pattern generation, precision timing results compression and diagnostics are all implemented in logic on the device. The firm’s original on-chip test technology, designated icBIST2.0, supported built-in self-test of logic and embedded memories. The latest release extends that on-chip test capability for at-speed test and diagnostics of complex system-on-a-chip devices. Designers will only consider such on-chip test capability if they are design million gate devices where 10,000 gates of embedded test functions represents less than 1 per cent of the silicon cost. The company claims that Sun Microsystems and Nortel are amongst those chip designers using its embedded ATE technology.

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